The formation of stacked nanowires is an important step for decreasing the feature sizes of semiconductor devices.
One issue which has to be tackled is to reduce the parasitic capacitance due to overlap between the gate and source-drain region of a transistor.
In order to minimize this parasitic capacitance, the formation of an internal spacer may be an integral part of the nanowire integration scheme.
Forming the internal spacer adds additional requirements to the methods for forming a semiconductor device comprising horizontal nanowires. There is therefore room for improvement in the existing methods for forming such semiconductor devices.